1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter and an output buffer are separately integrated to dramatically reduce a loss caused by a poor tape carrier package. Also, the present invention is directed to a data driving apparatus and method for a liquid crystal display wherein a digital to analog converter is driven on a time division basis to reduce the number of integrated circuits for providing a digital to analog conversion function.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged in such a manner as to cross each other. A liquid crystal cell is positioned at each intersection of the gate lines and the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line at a time. The data driver applies a data voltage signal to each of the data lines whenever the gate signal is applied to any one of the gate lines. The common voltage generator applies a common voltage signal to the common electrode. Accordingly, the LCD controls a light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the data voltage signal for each liquid crystal cell, to thereby display a picture. Each of the data drivers and gate drivers is formed from an integrated circuit (IC) chip. They are mounted in a tape carrier package (TCP) and connected to the liquid crystal display panel by a tape automated bonding (TAB) system mainly.
FIG. 1 schematically shows a data driving block in a conventional LCD.
Referring to FIG. 1, the data driving block includes data driving ICs 4 connected, via TCPs 6, to a liquid crystal display panel 2, and a data printed circuit board (PCB) 8 connected, via the TCPs 6, to the data driving ICs 4.
The data PCB 8 receives various control signals from a timing controller (not shown), and data signals and driving voltage signals from a power generator (not shown) to interface them to the data driving ICs 4. Each of the TCPs 6 is electrically connected to a data pad provided at the upper portion of the liquid crystal display panel 2 and an output pad provided at each data PCB 8. The data driving ICs 4 convert digital pixel data into analog pixel signals to apply them to data lines on the liquid crystal display panel 2.
To this end, as shown in FIG. 2, each of the data driving ICs 4 includes a shift register part 14 for applying a sequential sampling signal. A latch part 16 sequentially latches a pixel data VD in response to the sampling signal and outputs the pixel data VD at the same time. A digital to analog converter (DAC) 18 for converts the pixel data VD from the latch part 16 into a pixel signal. An output buffer part 26 buffers the pixel signal from the DAC 18 to output it. Further, the data driving ICs 4 each include a signal controller 10 for interfacing various control signals from a timing controller (not shown) and the pixel data VD. A gamma voltage part 12 supplies positive and negative gamma voltages required in the DAC 18. Each of the data driving ICs 4 drives n data lines DL1 to DLn.
The signal controller 10 controls various control signals such as, for example, SSP, SSC, SOE, REV and POL, and the pixel data VD to output them to the corresponding elements. The gamma voltage part 12 sub-divides several gamma reference voltages from a gamma reference voltage generator (not shown) for each gray level and outputs the sub-divided gamma reference voltges.
Shift registers included in the shift register part 14 sequentially shift a source start pulse SSP from the signal controller 10 in response to source sampling clock signal SSC to output the source start pulse SSP as a sampling signal.
A plurality of n latches included in the latch part 16 sequentially sample the pixel data VD from the signal controller 10 in response to the sampling signal from the shift register part 14 to latch it. Subsequently, the n latches respond to a source output enable signal SOE from the signal controller 10 to output the latched pixel data VD at the same time. In this case, the latch part 16 restores the pixel data VD modulated in such a manner to have a reduced transition bit number in response to a data inversion selecting signal REV and then outputs the pixel data VD. This is because the pixel data VD, having a transition bit number going beyond a reference value, is supplied such that it is modulated to have a reduced transition bit number in order to minimize an electromagnetic interference (EMI) upon data transmission from the timing controller.
The DAC 18 converts the pixel data VD from the latch part 16 into positive and negative pixel signals at the same time and outputs the signals. To this end, the DAC 18 includes a positive (P) decoding part 20 and a negative (N) decoding part 22, each of which are commonly connected to the latch part 16, and a multiplexor (MUX) 24 for selecting output signals of the P and N decoding parts 20 and 22.
A plurality of n P decoders, which are included in the P decoding part 20, convert n pixel data simultaneously inputted from the latch part 16 into positive pixel signals with the aid of positive gamma voltages from the gamma voltage part 12. A plurality of n N decoders, which are included in the N decoding part 22, convert n pixel data simultaneously inputted from the latch part 16 into negative pixel signals with the aid of negative gamma voltages from the gamma voltage part 12. The multiplexor 24 responds to a polarity control signal POL from the signal controller 10 to selectively output the positive pixel signals from the P decoding part 20 or the negative pixel signals from the N decoding part 22.
A plurality of n output buffers included in the output buffer part 26 consist of voltage followers which are connected to the n data lines DL1 to DLn in series. These output buffers buffer the pixel signals from the DAC 18 and apply the signals to the data lines DL1 to DLn.
As described above, each of the conventional data driving ICs 4 should have n latches and 2n decoders so as to drive n data lines DL1 to DLn. As a result, the conventional data driving IC 4 has a disadvantage in that it has a complex configuration and a relatively high manufacturing cost.
Furthermore, each of the conventional data driving ICs 4 is attached to the TCP 6 in a single chip to adhered to the liquid crystal display panel 2 and the data PCB 8 as shown in FIG. 1. Accordingly, the TCP has a high probability of, for example, breaking or short-circuiting. Thus, a large loss in costs results since the data driving ICs 4 mounted in the TCP 6 also cannot be used when the TCP 6 breaks or short-circuits.